This invention generally relates to a technique of computing the signal propagation delay in an LSI device and, more particularly, it relates to a technique that can effectively apply to a method of computing wiring capacitance and of computing cross talk delay that can get parasitic capacity depending on wiring at high speed and with great accuracy and that is capable of removing surplus margin at the time of delay prediction.
For example, as a technique that the present inventors have considered, when the signal propagation delay in a LSI designed is computed, it is necessary to determine the load capacity of the wiring of the LSI. Following methods are considered as methods of computing this wiring capacitance;
(a) A method of preparing a library of average capacity values per unit length, the values corresponding to width and wiring layer of the noted wiring, getting the length of the noted wiring from a netlist, and multiplying both capacity value per unit length and the length of the noted wiring to computing the noted wiring capacitance.
(b) A method of preparing a library of capacity values (Cbase) per unit length, the values corresponding to width and wiring layer of the noted wiring when the noted wiring is used alone, increments (xcex94Cpara) of capacity values of the noted wiring where there exists parallel wiring, and increments (xcex94Ccross) of capacity values of the noted wiring where there exists cross wiring, and getting the length of the noted wiring the lengths of the parallel wiring, and both width and number of the noted wiring from the netlist to compute the capacity of the noted wiring capacitance.
(c) A method of performing capacity simulation of the noted wiring per net.
As a method of computing the cross talk delay, for example, the Japanese Patent Application Laid-Open No. 9-147009 describes a technique of computing the signal propagation delay due cross talk. Briefly, it is a technique of determining the fluctuations in the signal propagation delay due to cross talk by referring to a function table expressing power of driving the gate (source impedance) and the locations and parallel lengths of the parallel wiring in order to predict the delay with great accuracy.
Thus, from a consequence of the inventors considering the above-mentioned computing methods of wiring capacitance, the following is apparent. As corresponding to the following, a problem about each method of said (a) and (b) will be explained.
(a) The fluctuations of the signal propagation delay cannot be expressed because the parasitic capacity is changed by high and low density resulting from arrangement of both adjacent wiring and upper-lower layer wiring. This prevents the computing of the delay form being performed with great accuracy.
(b) The values of Cbase, xcex94Cpara and xcex94Ccross have such a mutually depending relationship that values of xcex94cpara are different in high and low density of cross ratio of the cross wiring and those of xcex94ccross are different in depending on whether the adjacent wiring exists or not. Thereby, the values of Cbase, xcex94Cpara and xcex94ccross are very different from each other in selecting a model when the computing of the wiring capacitance is performed. Additionally, since this defines values of the selected model, the computed capacity values have a limit in accuracy.
(c) The operation of determining the capacity value by capacity simulation requires long time and a large memory capacity. Therefore, it is practically impossible to determine it within the period of real time that can be allowed for verifying the delay on the basis of the entire net. While methods for determining the capacity value at high speed by means of pseudo three-dimensional simulation are also used, such methods indispensably require a screening process of limiting critical paths before using them for the computation and hence cannot correspond to all the paths.
Therefore, an object of the present invention is to provide a method of computing at high speed and with great accuracy the parasitic capacity of an LSI device due to its wiring by particularly paying attention to the change in the parasitic capacity depending on high and low density of arrangement of both adjacent wiring and the upper-lower layer wiring, and is to provide a computer-readable recording medium storing the data necessary in the form of a library.
Additionally, the following is apparent about the method of computing the cross talk delay as mentioned above. That is, the operation of generating the fluctuations of the signal propagation delay as defined by the function table is limited only when the signal of a generated side is made operational within a predetermined period of time before and after the expected operating time of the signal of an affected side. However, the above described methods do not take this timing problem into consideration so that they inevitably involve the use of a surplus margin. Then, in order to reach a target of speed, power is raised to an unnecessary extent or the target speed is lowered and this consequently causes the performance of the LSI device to be lowered.
Thus, another object of the present invention is to provide a method of computing the delay due to cross talk by paying attention only to the cross talk noise that can give rise to fluctuations in the signal propagation delay so that the surplus margin may be eliminated when the delay is predicted. Still another object of the present invention is to provide a computer-readable recording medium storing the data in the form of a library.
The above-mentioned objects and other objects of the present invention as well as the novel features of the present invention will become apparent by reading the detailed description of the invention that follows below and also by referring to the accompanied drawings.
The characteristic aspects of the present invention can be summarized as follows.
According to the invention, there is provided a method of computing wiring capacitance of an LSI device comprising a step of determining parasitic capacity of the wiring of noted net from width and number of wires of other nets crossing the noted wiring of the net and the span of the wiring of other nets in the same layer and the upper and lower layers running in parallel with (adjacently relative to) the wiring of the noted net; said method being characterized in that the parasitic capacity of the wiring of the LSI device is determined on the basis of the wiring density of other nets existing around the wiring of noted net.
Preferably, in a method of computing wiring capacitance of an LSI device according to the invention, a table of wiring capacitance per unit length is generated as library in terms of the ratio of the wiring of upper-lower layers crossing wiring of the noted net (crossing ratio) relative to the length of the latter and that of the wiring of the same layer and the upper-lower layers running in parallel with the wiring of the noted net in order to determine the parasitic capacity of wiring within the LSI device.
Alternatively, in a method of computing wiring capacity of an LSI device according to the invention, a function of wiring capacitance per unit length is generated as library in terms of the ratio of wiring of upper-lower layers crossing wiring of noted net (crossing ratio) and that of the wiring of same layer and upper-lower layers running in parallel with the wiring of the noted net in order to determine the parasitic capacity of the wiring within the LSI device.
Then, the wiring of noted net is treated as a plurality of segments produced by dividing it on a via by via basis and the capacity of each segment is determined from the length of the segment, the span of the wiring of other nets in same layer and upper-lower layers running adjacently relative to the wiring and the value of widthxc3x97number of wiring crossing the wiring.
According to the invention, there is also provided a computer-readable recording medium storing data for a method of computing wiring capacity of an LSI device as defined above.
In an aspect of the invention, there is provided a method of computing the signal propagation delay due to cross talk of an LSI device comprising: a step of determining range of variation of the delay produced by the operating time of the signal of noted net and the cross talk noise; a step of determining the operating time of the signal of each net in the layer of the noted net, in the upper layer and in the lower having its wiring running in parallel with the wiring of the noted net and identifying the net having the range of fluctuation of the delay overlapping said range as noise source; a step of determining the variation of the delay from the table of variations of delay due to cross talk prepared in advance for the combination of the noted net and the net identified as noise source; and a step of adding the variation of the delay of the net identified as noise source to that of the delay of the noted net; said method being characterized by identifying the signal generating noise and operating within the range of variation of the delay due to cross talk and computationally determining the delay by considering only the variation of the delay due cross talk produced by the signal generating noise.
In a method of computing signal propagation delay due to cross talk, if a countermeasure allows a value of the delay about wiring of the noted net adding a value of fluctuation of net of the noise source, to attain an objective value, fluctuation of delay depending on the cross talk is prevented from occurring by means of at least one of modifications of wiring form about wiring of the noted net, modifications of form about net of the noise source, arrangement of shield wiring between wiring of the noted net and net of the noise source, and an insertion into gate to move outside range affected by fluctuation of the delay.
In a computer-readable recording medium storing data for the method of computing wiring capacitance, a library is formed from one of {combinations of a wiring layer and width between wiring of the noted net and wiring of other nets running in parallel therewith, and spaces between wiring and other wiring}, {combination of respective characteristics of wiring capacitance between wiring and other wiring running in parallel therewith, other capacity of non-noise signal wiring, other capacity of noise source signal wiring, resistance of non-noise signal wiring, and resistance of noise source signal source}, {location and parallel distance of parallel wiring}, and {combination of source impedance of both nets} in a table about value of fluctuation of the delay depending on the cross talk, and the data, representing the table in the library in a predetermined format, are stored.
Some remarkable advantages of the present invention include the following:
(1) According to a method of computing wiring capacitance of the present invention, the parasitic capacity depending on the wiring can be determine at high speed and with great accuracy, so that accuracy for computing the signal propagation time can be improved with great accuracy of computing the parasitic capacity.
(2) According to a method of computing the delay due to cross talk of the present invention, by means of taking into consideration only the cross talk noise causing really fluctuation of the delay, surplus margins can be removed at time of prediction of the delay, so that performance (operating speed) can be improved and consumption power can be reduced.
(3) As a result of (1) and (2) above, it is possible to improve the accuracy of computing the signal propagation time when designing a microprocessor, an ASIC or a high-speed LSI device by taking the signal propagation delay in the device into consideration in order to improve the performance and reduce the power consumption of the device.